The present invention relates generally to semiconductor integrated circuits. More particularly, it pertains to a compact system module with built-in thermoelectric cooling.
Integrated circuit technology relies on transistors to formulate vast arrays of functional circuits. The complexity of these circuits requires the use of an ever increasing number of linked transistors. As the number of transistors required increases, the integrated circuitry dimensions shrink. It is one objective in the semiconductor industry to construct transistors and other discrete devices which occupy less surface area on a given silicon chip/die. At the same time, the semiconductor industry seeks to increase the speed and power offered by integrated circuits. One approach to the latter challenge is through the development of improved methods for electrically connecting and packaging circuit devices which are fabricated on the same or on different silicon chips.
Ideally, we would like to build a computing system by fabricating all the necessary integrated circuits on one wafer or chip, as compared with today""s method of fabricating many chips of different functions and packaging them to assemble a system. A true xe2x80x9csystem on a chipxe2x80x9d would greatly improve integrated circuit performance and provide higher bandwidth. Unfortunately, it is very difficult with today""s technology to implement a truly high-performance xe2x80x9csystem on a chipxe2x80x9d because of vastly different fabrication processes and different manufacturing yields for the logic and memory circuits.
As a compromise, various xe2x80x9csystem modulesxe2x80x9d have been introduced that electrically connect and package circuit devices which are fabricated on the same or on different semiconductor chips. These began with simply stacking two semiconductor chips, e.g. a logic and memory chip, one on top of the other in an arrangement commonly referred to as chip-on-chip (COC) structure. Chip-on-chip structure most commonly utilizes micro bump bonding technology (MBB) to electrically connect the two chips. Several problems, however, remain inherent with this design structure. One serious complication includes the heating which occurs most seriously in connection with a logic chip such as a microprocessor. In high-performance microprocessors, where CPUs are running at 500 MHz and dissipating up to 85 watts of power, cooling becomes a crucial issue.
Usually, the cooling of such a package is accomplished by forced air. In certain applications, however, forced air cooling is not feasible or practical. Examples of such applications include computers to be used in outer space, in a vacuum environment on earth, or in clean rooms where air circulation is not desirable. For these and other instances, a different method of cooling is required. Another cooling method includes liquid cooling, such as the forced water cooling used in the thermal conduction modules of IBM main frame computers and forced freon cooling used in Cray supercomputers. Still, liquid cooling methods can also prove too bulky, costly, and not easily adapted for use in compact high-performance integrated circuit systems, e.g. portable devices.
Thus, it is desirable to develop an improved structure and method for cooling high performance integrated circuit systems. Additionally, the improved structure and method should accommodate a dense integration and packaging for semiconductor chips, e.g. logic and memory chips.
The above mentioned problems with integrated circuits and other problems are addressed by the present invention and will be understood by reading and studying the following specification. An integrated circuit package which accords improved performance is provided.
In particular, an improved integrated circuit package for providing built-in heating or cooling to a semiconductor chip is provided. The improved integrated circuit package provides increased operational bandwidth between different circuit devices, e.g. logic and memory chips. The improved integrated circuit package does not require changes in current CMOS processing techniques. The structure includes the use of a silicon interposer. The silicon interposer can consist of recycled rejected wafers from the front-end semiconductor processing. Micro-machined vias are formed through the silicon interposer. The micro-machined vias include electrical contacts which couple various integrated circuit devices located on the opposing surfaces of the silicon interposer. The packaging includes a Peltier element.
The Peltier element, using semiconductor-based materials, functions as a small heat pump. By applying a low-voltage d-c current to the Peltier element thermal energy is transferred with the effect that one portion of the Peltier element is cooled and another heated. In one embodiment, the heated portion of the Peltier element is in contact with a heat sink or the outer cover of the integrated circuit package and the cooled portion is in contact with a semiconductor chip. Thus providing improved cooling for high frequency, high speed microprocessor chip components. In an alternative embodiment, the arrangement is reversed. This design has no moving parts, is small in size and lightweight, and has the ability to cool below or heat above the ambient temperature surrounding integrated circuit devices.
These and other embodiments, aspects, advantages, and features of the present invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art by reference to the following description of the invention and referenced drawings or by practice of the invention. The aspects, advantages, and features of the invention are realized and attained by means of the instrumentalities, procedures, and combinations particularly pointed out in the appended claims.